A high level modeling system (HLMS) is an electronic design automation tool that allows a designer to create circuits and systems within a graphical design environment. Using a drag-and-drop paradigm, the designer may move graphic blocks, representing circuit components or functions, into the design environment. The designer may “draw” wires connecting the blocks to establish clocking and connectivity, e.g., signal flow, among the blocks.
Typically, an HLMS provides an architecture that allows plug-ins from different manufacturers to be used with the HLMS. Inclusion of these plug-ins allows the functionality of the HLMS to be extended. For example, an HLMS may allow a simulation engine to be used in conjunction with the HLMS. The simulation engine may provide a library of functions necessary to simulate hardware description language code. The simulation engine further may include software-based models of hardware components found within a particular type of programmable integrated circuit (IC) within which the circuit being developed will be implemented. This allows the HLMS to achieve greater accuracy during simulation.
To increase simulation performance, some simulation engines utilize Just-In-Time (JIT) compilation technology. JIT compilation refers to a process where portions of a computer program written in an interpretive language, e.g., a script or bytecode, can be compiled into native machine code for increased execution speed. The compilation typically is performed during execution of the interpretive program. While the runtime performance of the computer program will incur a penalty when portions of the program are compiled, typically this delay is overcome as the resulting native machine code executes much faster than its interpretive counterpart. Moreover, further performance gains are achieved each time the compiled code is executed as JIT compilation need be performed only one time during runtime of the simulation engine.
While using a simulation engine with an HLMS can provide a number of benefits, disadvantages do exist. For example, when a simulation engine runs as a plug-in of an HLMS, the two are still distinct entities. Typically the simulation engine will be implemented as a dynamically linked library (DLL). During runtime while the simulation engine executes, the HLMS and the simulation engine communicate through inter-process communication (IPC) and/or text-based communication. IPC refers to a set of techniques for the exchange of data among multiple threads in one or more processes, e.g., computer programs, executing within a computer. Depending upon the particular IPC technique used and the data exchanged, the latency between threads will vary, but still exists. This latency introduces inefficiencies into the simulation resulting in longer simulation times.
Because of the lack of integration between the simulation engine and the HLMS and the use of JIT compilation within the simulation engine, various internal states of the circuit design being simulated may not be observable during the simulation. The simulation engine must be instructed to write such information to a file. Only after simulation has completed execution may a developer view the contents of the file. This restriction can be inconvenient for the developer.
Another disadvantage of using an HLMS with a pluggable simulation engine is that the simulation engine is restricted to operating as a slave of the HLMS. The master, in this case the HLMS, must initiate all queries to the simulation engine and track the queries, e.g., monitor for responses, and perform the necessary “bookkeeping.” This relationship also introduces inefficiencies into the simulation.